- Optimization is everywhere: routing trucks, placing sensors on a farm, assigning jobs to machines, laying out chip components.
- Annealers help if your problem maps cleanly to an Ising/QUBO with a hardware-friendly graph.
- Gate-model (e.g., QAOA) helps when algorithmic structure matters and depth is manageable.
Where you’ll actually see it
Farm sensor placement
Pick N soil-moisture nodes to maximize coverage under a budget. Sparse couplings ⇒ good annealer fit if the field graph embeds well.
Warehouse routing
Multi-robot path planning with collision penalties. Dense constraints ⇒ embedding gets ugly; structured mixers in gate-model can encode rules.
Chip layout (toy)
Place blocks to minimize wire length. Local nets work with annealers; global timing constraints usually prefer gate-model heuristics.
Fit checklist
- Embedding Expected chain length and break rate (logical edges ÷ device edges).
- Penalty tuning Are constraints quadratic and well-scaled? Sensitivity of the answer to weights?
- Schedule knobs Pauses / reverse-anneal available? Calibration drift?
- Wall-clock Include I/O, sampling, and post-processing, not just device time.
One picture of the idea
Annealing slides from a simple landscape to your problem landscape. If the “valleys” are smooth and not too frustrated, it finds optimal solutions quickly. Rugged/glassy valleys or long chains make it struggle.
If/Then table
| If your instance looks like… | Then try… | Why |
|---|---|---|
| Sparse graph, local constraints | Annealer first | Embeds cleanly; short chains |
| Dense constraints / scheduling | Gate-model heuristic | Structured mixers can encode rules |
| Hard constraints via penalties | Both (weak-penalty sweep) | Compare feasibility and robustness |
Real-World Connection
Many problems become an Ising energy H = ∑ h_i s_i + ∑ J_{ij} s_i s_j with spins s_i∈{−1,+1}. Annealing turns a simple driver into this problem energy over time; gate-model QAOA alternates short “kicks” of both. What matters is how your constraints map to h and J, and whether the hardware graph can carry them.
Questions to put in an RFI
- Device graph, max chain length for your instance family, and observed chain-break rate
- Penalty choice, sensitivity analysis, robustness to noise
- Best classical baseline used and wall-clock methodology
- What proprietary or published optimization algorithms has your annealer implemented?